1. Field of the Invention
This invention relates generally to pseudo memory devices wherein DRAM is operated to function as SRAM, and more particularly, to a pseudo memory module having large memory capacity and being pin compatible with a pseudo memory device having a smaller memory capacity.
2. Description of the Background Art
Prior to discussing the structure and operation of a pseudo memory device in the prior art to which the invention is directed, some background on the structure and operation of the DRAM circuit is helpful. Thus, referring to FIG. 6, there is shown in a block diagram a prior art combination of a CPU, a DRAM and an interface circuit connected therebetween. Referring to FIG. 6, a DRAM 1 is connected to a multiplexer 2 adapted for affording sets of address signals by the combination of row and column address signals in the usual manner. A timing controller 3a is provided for affording a priority sequence among refresh request, a data readout request to the DRAM 1 and a data writing request to the DRAM 1. A control signal driver 3b is provided for producing control signals for the DRAM 1. A clock generator 6a is provided for producing clock signals supplied to CPU 5 for its operation and clock signals supplied to peripheral circuits for their synchronization. An address latch 7 is provided for latching only address signals outputted to an address data of the common bus of CPU 5. A data buffer 8 is provided for controlling the data input and output to and from the data bus of CPU 5.
The operation of the DRAM 1 responding to the access request from CPU 5 is explained. The timing controller 3a is responsive to the access request supplied from CPU 5 (status signal) to produce an operation control signal for DRAM 1. This operation control signal is supplied via control signal driver 3b to DRAM 1. The CPU 5 outputs address signals to the address data common bus. This address signal is latched in the address latch 7 and thence supplied to the address multiplexer 2. The address multiplexer 2 converts a serial address signals stored in parallel in address latch 7 into multiplexed address signal for controlling the DRAM 1 in a usual manner. The operation of accessing the DRAM 1 is performed in this manner. The data readout from DRAM 1 are supplied via data buffer 8 to CPU 5. The data buffer 8 is controlled by the timing controller 3a.
In the refreshing operation of the DRAM 1, the timing controller 3a is responsive to clock signals generated by clock generator 6a to produce refresh signals.
In the above described system shown in FIG. 6, interfacing circuits such as timing controller 3a or control signal driver 3b need be provided for cooperation with CPU 5 thereby complicating the peripheral circuits and enlarging the space necessary for providing the circuits.
A pseudo static RAM (PS RAM), or a virtual static RAM (VS RAM) commonly known to the prior art performs a function of SRAM using the DRAM. FIG. 7 is a schematic block diagram showing an example of the one-chip PS/VS RAM. An array of memory cell 1a includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and data are stored in each of the memory cells. A column decoder 1b and a row decoder 1c are provided for specifying an address of the memory cells of the array 1a and a sense amplifier ld is provided for reading out data in the memory cells. A refresh timer 3c is provided for setting an internal refresh time and a refresh counter 3e is provided for setting the timing of the refresh time by external control. An arbiter circuit 3f is provided for receiving refresh and access requests and determining the priority sequence among the requested operations. A clock generator 3g is provided for generating access requests. A column address buffer 9a is provided for temporarily storing column address signals and supplying the stored signals to the column decoder 1b. A row address buffer 9b temporarily stores the row address signals and supplies the stored signal to the row decoder 1c via arbiter circuit 3f.
Referring now to FIG. 7, the operation of one-chip PS/VS RAM is explained. When a CE signal from a CPU, not shown is applied to clock generator 3g, the clock generator 3g generates and access request signal. This access request signal is inputted to the arbiter circuit 3f where memory control signals are generated. The address signals are supplied to and latched in a latch circuit, not shown, from the address data common bus of the CPU, the output from the latch circuit being then introduced to the column address buffer 9a and the row address buffer 9b. The column address signal introduced into the column address buffer 9a designates the column address of the array of memory cells 1a via column decoder 1b, while the row address signal introduced into the row address buffer 9b is supplied to the array of memory cells 1a via arbiter circuit 3f and row decoder 1c to designate the row address.
The data to be written into the array of memory cells 1a are introduced via data input buffer 8a to the sense amplifier 1d, while the data readout from the array of memory cells 1a are outputted via output buffer 8b.
The refresh operation includes two kinds of operations, namely an external signal sync mode operation and an internal automatic mode operation. In the case of the external signal sync mode, the refresh operation is controlled by the refresh counter 3e, and, in the case of the internal automatic mode, the refresh operation is performed at a certain prescribed period by the arbiter circuit 3f acted by refresh timer 3c.
As described hereinabove, the one-chip PS/VS RAM shown in FIG. 7 includes in the form of one chip, all the portions of the circuit of FIG. 6 except for the CPU 5 and the address latch 7. Hence, an advantage is derived that the peripheral circuits may be simplified and the space necessary for mounting the circuit may be reduced. However, the memory capacity of one chip IC is limited. Moreover, the provision of complicated internal circuits results in increased cost per bit of the memory.
Furthermore, pseudo SRAM devices that currently are available have a common, or "standard", pin lay-out around which external circuit configurations are usually designed. Even if the memory capacity of pseudo SRAM device can be increased, it is desirable to retain the standard pin lay-out.